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Technology Value DLT

By Mike Van Dike

All drives use the DLT tape format of half-inch wide, at the time of occurrence of this format – it was the most common standard for magnetic tape. Using a tape width can increase the amount of recorded information. A distinctive feature of the DLT-devices is that the receiving reel tape is not in the cassette, and in the drive, which allows more efficient use of the volume of the cartridge. Size cartridge for all drives DLT-V/SDLT/DLT-S4 – 10×10 cm drive himself is somewhat larger. DLT drives read and write linearly to tape, and each track is written along with the data tapes.

When the end of tape head record is repositioned to another position on the tape and begins to record in the reverse direction. This process will occur as long as the tape is not be fully recorded. DLT technology was developed by Quantum, and has now split into two independent project – Value DLT and Super DLT. Figure 1 Ribbon nkopitel format Fig.2 DLT tape transport DLT-Drive Technology Super DLT (SDLT) is the successor to DLT, the developer – Quantum and DEC. It uses a different, more sophisticated tape, other magnetic head (CMR, a cluster of magnetoresistive heads), optical positioning system tracks, etc. You can still read compatibility with old Cartridges DLTIV for SDLT220/320; SDLT600 retain compatibility to read the ink cartridge SDLT I; DLT-S4 remains compatible to read the ink cartridge SDLT II. Fig.3 tape transport SDLT-drive the first device SDLT-220 (11/22 MB / s, 110/220 Gb), appeared in early 2001, Now comes the second SDLT320 (16/32 MB / s, 160/320 Gb), the third SDLT 600 (36/72 MB / s, 300/600 Gb) and fourth-generation DLT-S4 (60/120 MB / s, 800 / 1600Gb) respectively Technology Value DLT (DLT VS) is a side branch of DLT, the developer – Benchmark.

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CISC Architecture

By Mike Van Dike

The main disadvantage of processors based on the CISC architecture is the large number of possible ways to send data, which leads to a complication of operations using different addressing methods. All in CISC micro- processors have a different format, different number of operands, as well as different time for various instructions. Analysis of instruction set processors based on the CISC architecture, showed that most used in the programs (80%) CPU instructions are only 20% of all teams CISC processor, while 80% of teams underutilized. To solve the problems inherent in CISC architecture, we developed a new RISC architecture. Core calculator, made by RISC architecture contains a set of commonly used micro-due to what the calculator on a chip was made possible deployment of more general-purpose registers. The main advantages of RISC architecture is the presence of the following features: A large number of general-purpose registers.

Universal format for all instructions. Equal time execution of all instructions. Almost all of shipping operations Data carried on the route register – register. These features enable you to handle the flow of command instructions to a conveyor principle, ie synchronize hardware parts, taking into account serial transfer control from one hardware unit to another. Hardware blocks, allocated in the RISC architecture: Block loading of instructions includes the following components: instruction fetch block from memory instructions, instruction register, and places the instruction after the sampling and decoding unit instructions.

This stage is called the step sampling instructions. General purpose registers in conjunction with power management registers form the second stage of the pipeline that is responsible for reading the operands of instructions. The operands can be stored in the statement itself or in a general-purpose registers. This stage is called stage sampling operands. Arithmetic logic unit with control logic, which is based on the contents of the register instruction, determines the type carried out by the micro. The source of data in addition to instruction register can be instruction counter, when the micro-conditional or unconditional jump. This stage is called the executive stage pipeline. Set consisting of general purpose registers, logic, and sometimes write from RAM form a step of maintaining data. At this stage the result of the instructions are written in general purpose registers or in main memory.