CISC Architecture

The main disadvantage of processors based on the CISC architecture is the large number of possible ways to send data, which leads to a complication of operations using different addressing methods. All in CISC micro- processors have a different format, different number of operands, as well as different time for various instructions. Analysis of instruction set processors based on the CISC architecture, showed that most used in the programs (80%) CPU instructions are only 20% of all teams CISC processor, while 80% of teams underutilized. To solve the problems inherent in CISC architecture, we developed a new RISC architecture. Core calculator, made by RISC architecture contains a set of commonly used micro-due to what the calculator on a chip was made possible deployment of more general-purpose registers. The main advantages of RISC architecture is the presence of the following features: A large number of general-purpose registers.

Universal format for all instructions. Equal time execution of all instructions. Almost all of shipping operations Data carried on the route register – register. These features enable you to handle the flow of command instructions to a conveyor principle, ie synchronize hardware parts, taking into account serial transfer control from one hardware unit to another. Hardware blocks, allocated in the RISC architecture: Block loading of instructions includes the following components: instruction fetch block from memory instructions, instruction register, and places the instruction after the sampling and decoding unit instructions.

This stage is called the step sampling instructions. General purpose registers in conjunction with power management registers form the second stage of the pipeline that is responsible for reading the operands of instructions. The operands can be stored in the statement itself or in a general-purpose registers. This stage is called stage sampling operands. Arithmetic logic unit with control logic, which is based on the contents of the register instruction, determines the type carried out by the micro. The source of data in addition to instruction register can be instruction counter, when the micro-conditional or unconditional jump. This stage is called the executive stage pipeline. Set consisting of general purpose registers, logic, and sometimes write from RAM form a step of maintaining data. At this stage the result of the instructions are written in general purpose registers or in main memory.